Packaging Engineering Internship

About the role

Qorvo is seeking a Packaging Engineering Intern to support advanced packaging and substrate technology development within its Global Operations business group. The internship provides hands‑on experience with semiconductor assembly processes and exposure to senior leadership.

Key responsibilities

• Learn and contribute to advanced packaging and substrate technology development methodologies.
• Review assembly and marking diagrams to identify improvement opportunities.
• Plan and execute Design of Experiments to support project deployment.
• Perform onsite hands‑on semiconductor assembly tasks such as wire bonding, die attach, and flip‑chip processes.
• Document work and drive continuous‑improvement activities using Lean A3 reports.

Required profile

• Currently enrolled in a BS program in Materials Science, Chemical, Mechanical, or Electrical Engineering.
• Minimum 3.0 GPA.
• Background (theoretical or practical) with packaging materials such as solder, epoxy, flux, or mold compound.
• Familiarity with assembly processes like wire bond, die attach, or flip chip.
• Strong analytical, communication, and problem‑resolution skills.

Required skills

• Experience with PCG design software (e.g., Altium, KiCAD).

What we offer

• Challenging, skill‑building assignments.
• Mentoring and coaching from industry experts.
• Launch & Learns and other learning opportunities.
• Collaborative, team‑based work environment.
• Networking and social events.
• Final presentation to business leaders.
• Competitive hourly pay ($31‑$42/hr).