Design Verification Engineer (ASIC)

About the role

We are looking for a Design Verification Engineer with strong ASIC verification expertise to join our hardware development team. The role focuses on ensuring the functional correctness of complex SoC designs using industry‑standard methodologies.

Key responsibilities

• Develop and maintain verification environments for ASIC and SoC projects.
• Create verification plans based on functional specifications.
• Set up and run functional and gate‑level simulations, including regression testing.
• Perform coverage analysis and drive coverage closure.
• Debug simulation issues and collaborate with design engineers to resolve bugs.

Required profile

• Minimum 4 years of experience in ASIC verification.
• Hands‑on experience with at least two completed SoC verification projects.
• Proficiency in SystemVerilog and UVM methodology.
• Knowledge of one or more standard protocols such as Ethernet, PCIe, MIPI, USB, AXI, RISC‑V, AMBA or DDR.

Required skills

• ASIC verification methodologies
• SystemVerilog (SV)
• UVM framework
• Formal verification, mixed‑signal and power‑aware simulations
• Functional and gate‑level simulation debugging
• Verification plan development
• Regression setup and coverage analysis